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4-mbit (512k x 8) static ram cy62148ev30 mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05576 rev. *f revised april 18, 2007 features ? very high speed: 45 ns ? wide voltage range: 2.20v ? 3.60v ? pin compatible with cy62148dv30 ? ultra low standby power ? typical standby current: 1 a ? maximum standby current: 7 a (industrial) ? ultra low active power ? typical active current: 2 ma @ f = 1 mhz ? easy memory expansion with ce , and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? available in pb-free 36-ball vfbga, 32-pin tsop ii and 32-pin soic [1] packages functional description [2] the cy62148ev30 is a high performance cmos static ram organized as 512k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power do wn feature that significantly reduces power consumption. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high). the eight input and output pins (io 0 through io 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. data on the eight io pins (io 0 through io 7 ) is then written into the locati on specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the c ontents of the memory location specified by the address pins appear on the io pins. notes 1. soic package is available only in 55 ns speed bin. 2. for best practice recommendations, refer to the cypr ess application note ?system design guidelines? at http://www.cypress.com . logic block diagram a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe a 13 a 14 a 15 a 16 a 17 row decoder column decoder 512k x 8 array input buffer a 10 a 11 a 12 a 18 [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 2 of 12 pin configuration [1, 3] product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 (a) f = 1 mhz f = f max min typ [4] max typ [4] max typ [4] max typ [4] max cy62148ev30ll vfbga industrial 2.2 3.0 3.6 45 2 2.5 15 20 1 7 tsop ii cy62148ev30ll soic industrial 2.2 3.0 3.6 55 2 2.5 15 20 1 7 a 15 v cc a 13 a 12 a 5 nc we a 7 io 4 io 5 a 4 io 6 io 7 v ss a 11 a 10 a 1 v ss io 0 a 2 a 8 a 6 a 3 a 0 v cc io 1 io 2 io 3 a 17 a 18 a 16 ce oe a 9 a 14 d e b a c f g h nc 36-ball vfbga pinout top view 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 21 22 19 20 27 28 25 26 17 18 23 24 32-pin soic/tsop ii pinout top view a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 v ss v cc a 18 we oe ce notes 3. nc pins are not connected on the die. 4. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 3 of 12 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. ............ .......... 55c to +125c supply voltage to ground potential ....................... .................. ?0.3v to v cc(max) + 0.3v dc voltage applied to outputs in high-z state [5, 6] ........................ ?0.3v to v cc(max) + 0.3v dc input voltage [5, 6] .....................?0.3v to v cc(max) + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (mil-std-883, method 3015) latch up current..................................................... > 200 ma operating range product range ambient temperature v cc [7] cy62148ev30 industrial ?40c to +85c 2.2v to 3.6v electrical characteristics (over the operating range) parameter description test conditions 45 ns 55 ns [1] unit min typ [4] max min typ [4] max v oh output high voltage i oh = ?0.1 ma 2.0 2.0 v i oh = ?1.0 ma, v cc > 2.70v 2.4 2.4 v v ol output low voltage i ol = 0.1 ma 0.4 0.2 v i ol = 2.1 ma, v cc > 2.70v 0.4 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3v 1.8 v cc + 0.3v v v cc = 2.7v to 3.6v 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage v cc = 2.2v to 2.7v for vfbga and tsop ii package ?0.3 0.6 v for soic package ?0.3 0.4 [8] v v cc = 2.7v to 3.6v for vfbga and tsop ii package ?0.3 0.8 v for soic package ?0.3 0.6 [8] i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max), i out = 0 ma, cmos levels 15 20 15 20 ma f = 1 mhz 2 2.5 2 2.5 i sb1 automatic ce power down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v, v in < 0.2v f = f max (address and data only), f = 0 (oe and we ), v cc = 3.60v 17 17 a i sb2 [9] automatic ce power down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 17 17 a notes 5. v il(min) = ?2.0v for pulse durations less than 20 ns. 6. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 7. full device ac operation assumes a minimum of 100 s ramp time from 0 to v cc(min) and 200 s wait time after v cc stabilization. 8. under dc conditions the device meets a v il of 0.8v (for v cc range of 2.7v to 3.6v) and 0.6v (for v cc range of 2.2v to 2.7v). however, in dynamic conditions input low voltage applied to the device must not be higher than 0.6v and 0.4v for the above ranges. this is applicable to soic package only. please refer to an13470 for details. 9. only chip enable (ce ) must be high at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 4 of 12 capacitance (for all packages) [10] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance [10] parameter description test conditions vfbga package tsop ii package soic package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 72 75.13 55 c/w jc thermal resistance (junction to case) 8.86 8.95 22 c/w ac test loads and waveforms parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min typ [4] max unit v dr v cc for data retention 1.5 v i ccdr [9] data retention current v cc = 1.5v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 0.8 7 a t cdr [10] chip deselect to data retention time 0 ns t r [11] operation recovery time t rc ns data retention waveform v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 v cc(min) v cc(min) t cdr v dr > 1.5v data retention mode t r v cc ce notes 10. tested initially and after any design or proce ss changes that may affect these parameters. 11. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 5 of 12 switching characteristics (over the operating range) [12] parameter description 45 ns 55 ns [1] unit min max min max read cycle t rc read cycle time 45 55 ns t aa address to data valid 45 55 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 45 55 ns t doe oe low to data valid 22 25 ns t lzoe oe low to low z [13] 55ns t hzoe oe high to high z [13, 14] 18 20 ns t lzce ce low to low z [13] 10 10 ns t hzce ce high to high z [13, 14] 18 20 ns t pu ce low to power up 0 0 ns t pd ce high to power up 45 55 ns write cycle [15] t wc write cycle time 45 55 ns t sce ce low to write end 35 40 ns t aw address setup to write end 35 40 ns t ha address hold from write end 0 0 ns t sa address setup to write start 0 0 ns t pwe we pulse width 35 40 ns t sd data setup to write end 25 25 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [13, 14] 18 20 ns t lzwe we high to low z [13] 10 10 ns notes 12. test conditions for all parameters other than tri-state paramet ers assume signal transition time of 3 ns or less (1 v/ns), t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 13. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 14. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 15. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that ter minates the write. [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 6 of 12 switching waveforms read cycle no. 1 (address transition controlled) [16, 17] read cycle no. 2 (oe controlled) [17, 18] write cycle no. 1 (we controlled, oe high during write) [19, 20] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data io oe note 21 notes 16. device is continuously selected. oe , ce = v il . 17. we is high for read cycles. 18. address valid before or similar to ce transition low. 19. data io is high impedance if oe = v ih . 20. if ce goes high simultaneously with we high, the output remains in high impedance state. 21. during this period, the ios are in output state. do not apply input signals. [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 7 of 12 write cycle no. 2 (ce controlled) [19, 20] write cycle no. 3 (we controlled, oe low) [20] truth table ce we oe inputs/outputs mode power h x x high z deselect/power down standby (i sb ) l h l data out read active (i cc ) l h h high z output disabled active (i cc ) l l x data in write active (i cc ) switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data io we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data io note 21 [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 8 of 12 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62148EV30LL-45BVXI 51-85149 36-ball very fine pitch ball grid array (pb-free) industrial cy62148ev30ll-45zsxi 51-85095 32-pin thin small outline package ii (pb-free) 55 cy62148ev30ll-55sxi 51-85081 32-pin small ou tline integrated circuit (pb-free) contact your local cypress sales repres entative for availability of these parts. package diagrams figure 1. 36-ball vfbga (6 x 8 x 1 mm), 51-85149 a 1 a1 corner 0.75 0.75 ?0.300.05(36x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85149-*c [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 9 of 12 figure 2. 32-pin tsop ii, 51-85095 package diagrams (continued) 51-85095-** [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 10 of 12 ? cypress semiconductor corporation, 2007. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving , critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to th e user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 3. 32-pin (450 mil) molded soic, 51-85081 mobl is a registered trademark, and more battery life is a tr ademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 0.546[13.868] 0.440[11.176] 0.101[2.565] 0.050[1.270] 0.014[0.355] 0.118[2.997] 0.004[0.102] 0.047[1.193] 0.006[0.152] 0.023[0.584] 0.793[20.142] 0.450[11.430] 0.566[14.376] 0.111[2.819] 0.817[20.751] bsc. 0.020[0.508] min. max. 0.012[0.304] 0.039[0.990] 0.063[1.600] seating plane 1 16 17 32 0.004[0.102] 51-85081-*b [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 11 of 12 document history page document title: cy62148ev30 mobl ? , 4-mbit (512k x 8) static ram document number: 38-05576 rev. ecn no. issue date orig. of change description of change ** 223225 see ecn aju new data sheet *a 247373 see ecn syt changed from advance information to preliminary moved product portfolio to page 2 changed v cc stabilization time in footnote #7 from 100 s to 200 s changed i ccdr from 2.0 a to 2.5 a changed typo in data retention characteristics (t r ) from 100 s to t rc ns changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bin changed t hzoe , t hzwe from 12 to 15 ns for 35 ns speed bin and 15 to 18 ns for 45 ns speed bin changed t sce from 25 to 30 ns for 35 ns speed bin and 40 to 35 ns for 45 ns speed bin changed t hzce from 12 to 18 ns for 35 ns speed bin and 15 to 22 ns for 45 ns speed bin changed t sd from 15 to 18 ns for 35 ns speed bin and 20 to 22 ns for 45 ns speed bin changed t doe from 15 to 18 ns for 35 ns speed bin changed ordering information to include pb-free packages *b 414807 see ecn zsd changed from pr eliminary information to final changed the address of cypress semiconductor corporation on page #1 from ?3901 north first street? to ?198 champion court? removed 35ns speed bin removed ?l? versio n of cy62148ev30 changed ball c3 from dnu to nc. removed the redundant footnote on dnu. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f=1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max changed i sb1 and i sb2 typ values from 0.7 a to 1 a and max values from 2.5 a to 7 a. changed the ac test load capacitance value from 50pf to 30pf. changed i ccdr from 2.5 a to 7 a. added i ccdr typical value. changed t lzoe from 3 ns to 5 ns changed t lzce and t lzwe from 6 ns to 10 ns changed t hzce from 22 ns to 18 ns changed t pwe from 30 ns to 35 ns. changed t sd from 22 ns to 25 ns. updated the package diagram 36-pin vfbga from *b to *c added 32-pin soic package diagram and pin diagram updated the ordering information table and replaced the package name column with package diagram. *c 464503 see ecn nxr included automotive range in product offering updated thermal resistance table updated the ordering information *d 833080 see ecn vkn added footnote #8 added v il spec for soic package *e 890962 see ecn vkn removed automotive part and its related information added footnote #2 related to soic package added footnote #9 related to i sb2 added ac values for 55 ns industrial-soic range updated ordering information table [+] feedback [+] feedback
cy62148ev30 mobl ? document #: 38-05576 rev. *f page 12 of 12 *f 987940 see ecn vkn changed v ol spec from 0.4v to 0.2v for soic package at i ol = 0.1 ma changed v il spec from 0.6v to 0.4v for soic package at v cc = 2.2v to 2.7v updated footnote #8 made footnote #9 applicable for both i sb2 and i ccdr document title: cy62148ev30 mobl ? , 4-mbit (512k x 8) static ram document number: 38-05576 rev. ecn no. issue date orig. of change description of change [+] feedback [+] feedback

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